Field effect transistors (FETs) typically include a semiconductor material having a channel region formed between a source region and a drain region. A conductivity of the channel region can be controlled according to a voltage applied to a control gate. To better understand various features of the disclosed embodiments, a conventional junction FET will now be described.
Referring to FIGS. 14A to 14C, a conventional JFET is shown in a series of views and designated by the general reference character 1400. FIG. 14A is a top plan view. FIG. 14B is a side cross sectional view taken along line B-B of FIG. 14A. FIG. 14C is a side cross sectional view taken along line C-C of FIG. 14A.
Conventional JFET 1400 can include a gate 1402, a channel 1404, a source 1406, and a drain 1408. All of these regions (1402 to 1408) can be formed within a silicon substrate 1410. The particular conventional JFET 1400 shown is a p-channel JFET, thus a channel 1404, source 1406, and drain 1408 can be p-doped regions, while a gate 1402 can be an n-doped region. Conventional JFET 1400 can be formed in an active region 1412 that can be an n-doped region.
Electrical contact with source 1406 and drain 1408 can be made by metal source contact 1414 and metal drain contact 1416.
As shown in FIG. 14C, a metal gate contact 1418 can make electrical contact with a gate contact diffusion 1420. Such an arrangement can enable gate 1402 and active region 1412 to be commonly driven by metal gate contact 1418.
In addition to conventional silicon-based JFET, transistors based on other semiconductor materials are known. As but one example, a metal epitaxial semiconductor FET (MESFET) can be formed on a gallium arsenide (GaAs) substrate. In such an arrangement, a bulk region formed below a channel can serve as an insulating layer. That is, such a conventional GaAs transistor includes a top gate, but not a bottom gate.